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400khz 2-wire serial e 2 prom with block lock tm 64k 8k x 8 bit ? xicor, 1995, 1996 patents pending characteristics subject to change without notice 7038-1.2 4/25/97 t0/c2/d0 sh 1 x24640 functional diagram features ? save critical data with programmable block lock protection ?block lock (0, 1/4, 1/2, or all of e 2 prom array) ?software program protection ? programmable hardware write protect ? in circuit programmable rom mode ? 400khz 2-wire serial interface ? schmitt trigger input noise suppression ?output slope control for ground bounce noise elimination ? longer battery life with lower power ? active read current less than 1ma ?active program current less than 3ma ? standby current less than 1 a ? 1.8v to 3.6v, 2.5v to 5.5v and 4.5v to 5.5v power supply versi ons ? 32 word page write mode ? minimizes total write time per word ? internally organized 8k x 8 ? bidirectional data transfer protocol ? self-timed write cycle ? typical write cycle time of 5ms ? high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? 8-lead soic ? 20-lead tssop ? 8-lead pdip description the x24640 is a cmos serial e 2 prom, internally organized 8k x 8. the device features a seri al inter- face and software protocol allowing operation on a simple two wire bus. the bus operates at 400 khz al l the way down to 1.8v. three device select inputs (s 0 ?s 2 ) allow up to eight devices to share a common two wire bus. a write protect register at the highest address loc ation, ffffh, provides three write protection feature s: software write protect, block lock protect, and programmable hardware write protect. the software write protect feature prevents any nonvolatile writ es to the device until the wel bit in the write prote ct register is set. the block lock protection feature gives the user four array block protect options, set by programming two bits in the write protect re gister. the programmable hardware write protect feature allows the user to install the device with wp tied to v cc , program and block lock the desired portions of the memory array in circuit, and then enable the in circuit programmable rom mode by programming the wpen bit in the write protect register. after this, the block locked portions of the array, including the w rite protect register itself, are permanently protected from being erased. serial e 2 prom data and address (sda) scl s2 s1 s0 wp command decode and control logic block lock and write protect control logic device select logic write protect register page decode logic data register y decode logic 2k x 8 2k x 8 4k x 8 write voltage control serial e 2 prom array 8k x 8 7038 fm 01 this x24640 device has been acquired by ic microsystems from xicor, inc. ic mic ic microsystems tm
x24640 2 xicor e 2 pr oms are designed and tested f or applica- tions requir ing e xtended endur ance . inherent data retention is g reater than 100 y ears . pin descriptions serial clock (scl) the scl input is used to cloc k all data into and out of the de vice . serial data (sda) sd a is a bidirectional pin used to tr ansf er data into and out of the de vice . it is an open dr ain output and ma y be wire-ored with an y n umber of open dr ain or open collector outputs . an open dr ain output requires the use of a pull-up resistor . f or selecting typical v alues , ref er to the pull- up resistor selection g r aph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the de vice select inputs (s 0 , s 1 , s 2 ) are used to set the rst three bits of the 8-bit sla v e address . this allo ws up to eight de vices to share a common b us . these inputs can be static or activ ely dr iv en. if used statically the y m ust be tied to v ss or v cc as appro- pr iate . if activ ely dr iv en, the y m ust be dr iv en with cmos le v els (dr iv en to v cc or v ss ). write protect (wp) the wr ite protect input controls the hardw are wr ite protect f eature . when held lo w , hardw are wr ite protection is disab led. when this input is held high, and the wpen bit in the wr ite protect register is set high, the wr ite protect register is protected, pre v enting changes to the bloc k loc k protection and wpen bits . pin names 7038 fm t01 pin configuration symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage nc no connect v cc wp scl sd a s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 x24640 8-lead pdip/soic 7038 fm 02 * .244 * .197 not to scale nc s 0 s 1 nc nc nc s 2 v ss nc nc nc v cc wp nc nc nc scl sda nc nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 x24640 0.300" max 0.252" 20-lead tssop * soic measurement
x24640 3 device operation the de vice suppor ts a bidirectional b us or iented protocol. the protocol de nes an y de vice that sends data onto the b us as a tr ansmitter , and the receiving de vice as the receiv er . the de vice controlling the tr ansf er is a master and the de vice being controlled is the sla v e . the master will alw a ys initiate data tr ans- f ers , and pro vide the cloc k f or both tr ansmit and receiv e oper ations . theref ore , the de vice will be considered a sla v e in all applications . clock and data conventions data states on the sd a line can change only dur ing scl lo w . sd a state changes dur ing scl high are reser v ed f or indicating star t and stop conditions . ref er to figures 1 and 2. start condition all commands are preceded b y the star t condition, which is a high to lo w tr ansition of sd a when scl is high. the de vice contin uously monitors the sd a and scl lines f or the star t condition and will not respond to an y command until this condition has been met. scl sd a d a t a st able data change 7038 fm 03 scl sd a st ar t bit st op bit 7038 fm 04 figure 1. data validity figure 2. definition of start and stop
x24640 4 figure 3. acknowledge response from receiver stop condition all comm unications m ust be ter minated b y a stop condition, which is a lo w to high tr ansition of sd a when scl is high. the stop condition is also used to place the de vice into the standb y po w er mode after a read sequence . a stop condition can only be issued after the tr ansmitting de vice has released the b us . acknowledge ac kno wledge is a softw are con v ention used to indicate successful data tr ansf er . the tr ansmitting de vice , either master or sla v e , will release the b us after tr ans- mitting eight bits . dur ing the ninth cloc k cycle the receiv er will pull the sd a line lo w to ac kno wledge that it receiv ed the eight bits of data. ref er to figure 3. the de vice will respond with an ac kno wledge after recognition of a star t condition and its sla v e address . if both the de vice and a wr ite oper ation ha v e been selected, the de vice will respond with an ac kno wledge after the receipt of each subsequent 8-bit w ord. in the read mode the de vice will tr ansmit eight bits of data, release the sd a line and monitor the line f or an ac kno wledge . if an ac kno wledge is detected and no stop condition is gener ated b y the master , the de vice will contin ue to tr ansmit data. if an ac kno wledge is not detected, the de vice will ter minate fur ther data tr ans- missions . the master m ust then issue a stop condition to retur n the de vice to the standb y po w er mode and place the de vice into a kno wn state . scl fr om master d a t a output fr om transmitter 1 8 9 data output fr om receiver st ar t a ckno wledge 7038 fm 05
x24640 5 figure 4. device addressing 1 s 1 s 0 r / w device select 0 1 0 s 2 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 d a t a byte a2 a1 a0 a5 lo w order w ord address a4 a3 word address byte 0 0 a10 a9 a8 0 high order w ord address a11 x24640 w ord address byte 1 0 a12 a7 a6 d0 7038 fm 06 device addressing f ollo wing a star t condition, the master m ust output the address of the sla v e it is accessing. the rst f our bits of the sla v e address byte are the de vice type identi er bits . these m ust equal ?010? the ne xt 3 bits are the de vice select bits s 0 , s 1 , and s 2 . this allo ws up to 8 de vices to share a single b us . these bits are compared to the s 0 , s 1 , and s 2 de vice select input pins . the last bit of the sla v e address byte de nes the oper ation to be perf or med. when the r/ w bit is a one , then a read oper ation is selected. when it is z ero then a wr ite oper ation is selected. ref er to gure 4. after loading the sla v e address byte from the sd a b us , the de vice compares the de vice type bits with the v alue ?010 and the de vice select bits with the status of the de vice select input pins . if the compare is not successful, no ac kno wledge is output dur ing the ninth cloc k cycle and the de vice retur ns to the standb y mode . the w ord address is either supplied b y the master or obtained from an inter nal counter , depending on the oper ation. the master m ust supply the tw o w ord address bytes as sho wn in gure 4. the inter nal organization of the e 2 arr a y is 256 pages b y 32 b ytes per page . the page address is par tially contained in the w ord address byte 1 and par tially in bits 7 through 5 of the w ord address byte 0. the b yte address is contained in bits 4 through 0 of the w ord address byte 0. see gure 4.
x24640 6 figure 6. page write sequence write operations byte write f or a wr ite oper ation, the de vice requires the sla v e address byte , the w ord address byte 1, and the w ord address byte 0, which giv es the master access to an y one of the w ords in the arr a y . upon receipt of the w ord address byte 0, the de vice responds with an ac kno wl- edge , and w aits f or the rst eight bits of data. after receiving the 8 bits of the data b yte , the de vice again responds with an ac kno wledge . the master then ter minates the tr ansf er b y gener ating a stop condition, at which time the de vice begins the inter nal wr ite cycle to the non v olatile memor y . while the inter nal wr ite cycle is in prog ress the de vice inputs are disab led and the de vice will not respond to an y requests from the master . the sd a pin is at high impedance . see gure 5. page write the de vice is capab le of a thir ty-tw o b yte page wr ite oper ation. it is initiated in the same manner as the b yte wr ite oper ation; b ut instead of ter minating the wr ite oper ation after the rst data w ord is tr ansf erred, the master can tr ansmit up to thir ty-one more w ords . the de vice will respond with an ac kno wledge after the receipt of each w ord, and then the b yte address is inter nally incremented b y one . the page address remains constant. when the counter reaches the end of the page , it ?olls o v er and goes bac k to the rst b yte of the current page . this means that the master can wr ite 32 w ords to the page beginning at an y b yte . if the master begins wr iting at b yte 16, and loads 32 w ords , then the rst 16 w ords are wr itten to b ytes 16 through 31, and the last 16 w ords are wr itten to b ytes 0 through 15. afterw ards , the address counter w ould point to b yte 16. if the master wr ites more than 32 w ords , then the pre viously loaded data is o v erwr itten b y the ne w data, one b yte at a time . the master ter minates the data b yte loading b y issuing a stop condition, which causes the de vice to begin the non v olatile wr ite cycle . as with the b yte wr ite oper ation, all inputs are disab led until completion of the inter nal wr ite cycle . ref er to gure 6 f or the address , ac kno wledge , and data tr ansf er sequence . s t a r t sla ve address s t o p a c k a c k a c k a c k a c k data (0) signals fr om the master sd a b us signals fr om the sla ve (n) w ord address byte 1 w ord address byte 0 0 s p data 1 0 1 0 (0 n 31) 7038 fm 08 figure 5. byte write sequence signals fr om the master sd a b us signals fr om the sla ve s t a r t sla ve address s t o p a c k a c k a c k a c k w ord address byte 1 d a t a 1 0 1 0 0 w ord address byte 0 s p 7038 fm 07
x24640 7 acknowledge polling the maxim um wr ite cycle time can be signi cantly reduced using ac kno wledge p olling. t o initiate ac kno wledge p olling, the master issues a star t condi- tion f ollo w ed b y the sla v e address byte f or a wr ite or read oper ation. if the de vice is still b usy with the inter nal wr ite cycle , then no a ck will be retur ned. if the de vice has completed the inter nal wr ite oper ation, an a ck will be retur ned and the host can then proceed with the read or wr ite oper ation. ref er to gure 7. byte lo ad completed by issuing st op . enter a ck polling issue st ar t issue sla ve address byte (read or write) a ck returned? high v ol t a ge cycle complete. continue seq uence? continue normal read or write command seq uence pr oceed issue st op no yes yes issue st op no 7038 fm 09 read operations read oper ations are initiated in the same manner as wr ite oper ations with the e xception that the r/ w bit of the sla v e address byte is set to one . there are three basic read oper ations: current address reads , random reads , and sequential reads . current address read inter nally , the de vice contains an address counter that maintains the address of the last w ord read or wr itten incremented b y one . after a read oper ation from the last address in the arr a y , the counter will ?oll o v er to the rst address in the arr a y . after a wr ite oper ation to the last address in a giv en page , the counter will ?oll o v er to the rst address on the same page . upon receipt of the sla v e address byte with the r/ w bit set to one , the de vice issues an ac kno wledge and then tr ansmits the eight bits of the data byte . the master ter minates the read oper ation when it does not respond with an ac kno wledge dur ing the ninth cloc k and then issues a stop condition. ref er to gure 8 f or the address , ac kno wledge , and data tr ansf er sequence . it should be noted that the ninth cloc k cycle of the read oper ation is not a ?on? care . t o ter minate a read oper ation, the master m ust either issue a stop condi- tion dur ing the ninth cycle or hold sd a high dur ing the ninth cloc k cycle and then issue a stop condition. from the s t a r t sla ve address s t o p a c k data signals from the master sda bus signals slave 1 s p 0 1 0 1 7038 fm 10 figure 7. acknowledge polling sequence figure 8. current address read sequence
x24640 8 random read random read oper ation allo ws the master to access an y memor y location in the arr a y . pr ior to issuing the sla v e address byte with the r/ w bit set to one , the master m ust rst perf or m a ?umm y wr ite oper ation. the master issues the star t condition and the sla v e address byte with the r/ w bit lo w , receiv es an ac kno wledge , then issues the w ord address byte 1, receiv es another ac kno wledge , then issues the w ord address byte 0. after the de vice ac kno wledges receipt of the w ord address byte 0, the master issues another star t condition and the sla v e address byte with the r/ w bit set to one . this is f ollo w ed b y an ac kno wledge and then eight bits of data from the de vice . the master ter minates the read oper ation b y not responding with an ac kno wledge and then issuing a stop condition. ref er to gure 9 f or the address , ac kno wledge , and data tr ansf er sequence . the de vice will perf or m a similar oper ation called ?et current address if a stop is issued instead of the second star t sho wn in gure 9. the de vice will go into standb y mode after the stop and all b us activity will be ignored until a star t is detected. the eff ect of this oper- ation is that the ne w address is loaded into the address counter , b ut no data is output b y the de vice . the ne xt current address read oper ation will read from the ne wly loaded address . sequential read sequential reads can be initiated as either a current address read or r andom read. the rst data byte is tr ansmitted as with the other modes; ho w e v er , the master no w responds with an ac kno wledge , indicating it requires additional data. the de vice contin ues to output data f or each ac kno wledge receiv ed. the master ter minates the read oper ation b y not responding with an ac kno wledge and then issuing a stop condition. the data output is sequential, with the data from address n f ollo w ed b y the data from address n + 1. the address counter f or read oper ations increments through all b yte addresses , allo wing the entire memor y contents to be read dur ing one oper ation. at the end of the address space the counter ?olls o v er to address 0000h and the de vice contin ues to output data f or each ac kno wledge receiv ed. ref er to gure 10 f or the ac kno wledge and data tr ansf er sequence . sla ve address s s t o p a c k a c k a c k a c k d a t a (1) d a t a (2) signals from the master sda bus signals from the slave d a t a (n?) d a t a (n) 1 (n is an y integer g reater than 1) p 7038 fm 12 signals fr om the master sd a b us signals fr om the sla ve s t a r t sla ve address s t o p a c k a c k a c k w ord address byte 1 sla ve address 0 w ord address byte 0 s t a r t 1 d a t a a c k s p s 1 0 1 0 7038 fm 11 figure 9. random read sequence figure 10. sequential read sequence
x24640 9 write protect register (wpr) writing to the write protect register the wr ite protect register can only be modi ed b y perf or ming a ?yte wr ite oper ation directly to the address ffffh as descr ibed belo w . the data byte m ust contain z eroes where indicated in the procedur al descr iptions belo w; otherwise the oper- ation will not be perf or med. only one data byte is allo w ed f or each register wr ite oper ation. the par t will not ac kno wledge an y data b ytes after the rst b yte is entered. the user then has to issue a stop to initiate the non v olatile wr ite cycle that wr ites bl0, bl1, and wpen to the non v olatile bits . a stop m ust also be issued after v olatile register wr ite oper ations to put the de vice into standb y . the state of the wr ite protect register can be read b y perf or ming a r andom b yte read at ffffh at an y time . the par t will reset itself after the rst b yte is read. the master should supply a stop condition to be consistent with the protocol, b ut a stop is not required to end this oper ation. after the read, the address counter contains 0000h. write protect register: wpr (addr = ffff h ) wel: write enable latch (volatile) 0 = wr ite enab le latch reset, wr ites disab led. 1 = wr ite enab le latch set, wr ites enab led. rwel: register write enable latch (volatile) 0 = register wr ite enab le latch reset, wr ites to the wr ite protect register disab led. 1 = register wr ite enab le latch set, wr ites to the wr ite protect register enab led. bl0, bl1: block lock protect bits (nonvolatile) the bloc k loc k protect bits , bl0 and bl1, deter mine which b loc ks of the arr a y are protected. a wr ite to a protected b loc k of memor y is ignored, b ut will receiv e an ac kno wledge . the master m ust issue a stop to put the par t into standb y , just as it w ould f or a v alid wr ite; b ut the stop will not initiate an inter nal non v olatile wr ite cycle . see gure 11. wpen: write protect enable bit (nonvolatile) the wr ite protect ( wp ) pin and the wr ite protect enab le (wpen) bit in the wr ite protect register control the prog r ammab le hardw are wr ite protection f eature . hardw are wr ite protection is enab led when the wp pin is high and the wpen bit is high, and disab led when either the wp pin is lo w or the wpen bit is lo w . figure 12 de nes the wr ite protect status f or each combination of wpen and wp . when the chip is hardw are wr ite protected, non v olatile wr ites are disab led to the wr ite protect register , including the bloc k loc k protect bits and the wpen bit itself , as w ell as to the bloc k loc k protected sections in the memor y arr a y . only the sections of the memor y arr a y that are not bloc k loc k protected, and the v olatile bits wel and r wel, can be wr itten. in circuit programmable rom mode note that when the wpen bit is wr ite protected, it cannot be changed bac k to a lo w state; so wr ite protection is enab led as long as the wp pin is held high. thus an in circuit prog r ammab le r om function can be implemented b y hardwir ing the wp pin to v cc , wr iting to and bloc k loc king the desired por tion of the arr a y to be r om, and then prog r amming the wpen bit high. unused bit positions bits 0, 5 & 6 are not used. all wr ites to the wpr m ust ha v e z eros in these bit positions . the data b yte output dur ing a wpr read will contain z eros in these bits . writing to the wel and rwel bits wel and r wel are v olatile latches that po w er up in the lo w (disab led) state . while the wel bit is lo w , wr ites to an y address other than ffffh will be ignored (no ac kno wledge will be issued after the data byte). the wel bit is set b y wr iting 00000010 to address ffffh. once set, wel remains high until either it is reset to 0 (b y wr iting 00000000 to ffffh) or until the par t po w ers up again. wr ites to wel and r wel do not cause a non v olatile wr ite cycle , so the de vice is ready f or the ne xt oper ation immediately after the stop condition. the r wel bit controls wr ites to the bloc k loc k protect bits , bl0 and bl1, and the wpen bit. if r wel is 0 then no wr ites can be perf or med on bl0, bl1, or wpen. r wel is reset when the de vice po w ers up or after an y non v olatile wr ite , including wr ites to the bloc k loc k protect bits , wpen bit, or an y b ytes in the memor y arr a y . when r wel is set, wel cannot be 7 6 5 4 3 2 1 0 wpen 0 0 bl1 bl0 r wel wel 0
x24640 10 reset, nor can r wel and wel be reset in one wr ite oper ation. r wel can be reset b y wr iting 00000010 to ffffh; b ut this is the same oper ation as in step 3 descr ibed belo w , and will result in prog r aming bl0, bl1, and wpen. writing to the bl and wpen bits a 3 step sequence is required to change the non v ola- tile bloc k loc k protect or wr ite protect enab le bits: 1) set wel=1, wr ite 00000010 to address ffffh (v olatile wr ite cycle .) 2) set r wel=1, wr ite 00000110 to address ffffh (v olatile wr ite cycle .) 3) set bl1, bl0, and/or wpen bits , wr ite u00xy010 to address ffffh, where u=wpen, x=bl1, and y=bl0. (non v olatile wr ite cycle .) the three step sequence w as created to mak e it dif - cult to change the contents of the wr ite protect register accidentally . if wel w as set to one b y a pre vious register wr ite oper ation, the user ma y star t at step 2. r wel is reset to z ero in step 3 so that user is required to perf or m steps 2 and 3 to mak e another change . r wel m ust be 0 in step 3. if the r wel bit in the data b yte f or step 3 is a one , then no changes are made to the wr ite protect register and the de vice remains at step 2. the wp pin m ust be lo w or the wpen bit m ust be lo w bef ore a non v olatile register wr ite oper ation is initiated. otherwise , the wr ite oper ation will abor t and the de vice will go into standb y mode after the master issues the stop condition in step 3. step 3 is a non v olatile wr ite oper ation, requir ing t wc to complete (ac kno wledge polling ma y be used to reduce this time requirement). it should be noted that step 3 must end with a stop condition. if a star t condition is issued dur ing or at the end of step 3 (instead of a stop condition) the de vice will abor t the non v olatile register wr ite and remain at step 2. if the oper ation is abor ted with a star t condition, the master m ust issue a stop to put the de vice into standb y mode . figure 11. block lock protect bits and protected addresses 7038 frm t02 figure 12. wp pin and wpen bit functionality 7038 frm t03 bl1 bl0 pr otected ad dresses arra y location 0 0 none no protect 0 1 1800h - 1fffh upper 1/4 1 0 1000h - 1fffh upper 1/2 1 1 0000h - 1fffh full arr a y wp wpen memor y arra y not loc k bloc k pr otected memor y arra y bloc k loc k pr otected bloc k loc k bits wpen bit 0 x wr itab le protected unprotected unprotected x 0 wr itab le protected unprotected unprotected 1 1 wr itab le protected protected protected
x24640 11 absolute maximum ratings* temperature under bias x24640 ....................................... ?5 c to +135 c storage temperature ........................ ?5 c to +150 c voltage on any pin with respect to v ss .................................... ?v to +7v d.c. output current .............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c d.c. operating characteristics 7038 frm t06 capacitance t a = +25 c , f = 1mhz, v cc = 5v 7038 frm t07 notes: (1) must perf or m a stop command pr ior to measurement. (2) v il min. and v ih max. are f or ref erence only and are not 100% tested. (3) this par ameter is per iodically sampled and not 100% tested. limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 400khz, sda = open, all other inputs = v ss or v cc ?0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 5 m a scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 m a scl = sda = v cc , all other inputs = v ss or v cc ?0.3v, v cc = 2.5v i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (2) input low voltage ?.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma v hys (3) hysteresis of schmitt trigger inputs v cc x 0.05 v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl, wp) 6 pf v in = 0v recommended operating conditions 7038 frm t04 temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c 7038 frm t05 supply voltage limits x24640 4.5v to 5.5v x24640?.5 2.5v to 5.5v x24640?.8 1.8v to 3.6v *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those indicated in the oper ational sections of this speci cation is not implied. exposure to absolute maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
x24640 12 a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits 7038 frm t09 power-up timing (4) 7038 frm t10 notes: (4) t pur and t puw are the dela ys required from the time v cc is stab le until the speci ed oper ation can be initiated. these par ameters are per iodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.2 m s t hd:sta start condition hold time 0.6 m s t low clock low period 1.2 m s t high clock high period 0.6 m s t su:sta start condition setup time (for a repeated start condition) 0.6 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 100 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 m s t dh data out hold time 50 300 ns t of output fall time 20+0.1c b (5) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. conditions of test 7038 frm t08 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 5v 1.53k w 100pf output 7038 fm 13
x24640 13 symbol table w a veform inputs outputs must be steady will be steady may change from lo w to high will change from lo w to high may change from high to low will change from high to low don? care: changes allo wed changing: state not kno wn n/a center line is high impedance 7038 fm 17 the wr ite cycle time is the time from a v alid stop condition of a wr ite sequence to the end of the inter nal er ase/ prog r am cycle . dur ing the wr ite cycle , the x24640 b us interf ace circuits are disab led, sd a is allo w ed to remain high, and the de vice does not respond to its sla v e address . bus timing t su:st a t hd:st a t hd:d a t t su:d a t t lo w t su:st o t r t b uf scl sd a in sd a out t dh t aa t f t high 7038 fm 14 write cycle limits 7038 frm t11 symbol parameter min. typ. (5) max. units t wc (6) write cycle time 5 10 ms scl sd a 8th bit w ord n a ck t wc st op condition st ar t condition 7038 fm 15 guidelines for calculating typical values of bus pull-up resistors 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resist ance max. resist ance r max = c b us t r r min = i ol min v cc max =1.8k w 7038 fm 16 bus timing notes: (5) t ypical v alues are f or t a = 25 c and nominal supply v oltage (5v). (6) t wr is the minim um cycle time to be allo w ed from the system perspectiv e unless polling techniques are used. it is the maxim um time the de vice requires to automatically complete the inter nal wr ite oper ation.
x24640 14 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing p ackage type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint 7038 fm 19
x24640 15 packaging information note: all dimensions in inches (in p arentheses in millimeters) 20-lead plastic, tssop p ackage type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .260 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) see detail ? .031 (.80) .041 (1.05) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x24640 16 packaging information no te: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.1 10 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref . pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 sea ting plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic du al in-line p a cka ge type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) 7040 fm 18
x24640 17 ordering information part mark convention device x24640 p t g - v blank = 8-lead soic blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?40 c to +85 c ae = 2.5v to 5.5v, 0 c to +70 c af = 2.5v to 5.5v, ?40 c to +85 c x24640 x g x limited warranty devices sold by xicor, inc. are covered by the warr anty and patent indemnification provisions appearin g in its terms of sale only. xicor, inc. makes no warranty, express, statuto ry, implied, or by description regarding the inform ation set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xico r, inc. reserves the right to discontinue productio n and change specifications and prices at any time an d without notice. xicor, inc. assumes no responsibility for the use o f any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, li cense s are implied. u.s. patents xicor products are covered by one or more of the follo wing u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,5 33,846; 4,599,706; 4,617,652; 4,668,932; 4,752, 912; 4,829, 482; 4,874, 967; 4,883, 976. foreig n patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this pro duct should design the system with appropriate error detection and correction, redunda ncy and back-up features to prevent such an occuren ce. xicor's products are not authorized for use in crit ical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical impla nt into the body, or (b) support or sustain life, and whose failure to perform, when properly u sed in accordance with instructions for use provide d in the labeling, can be reason ably expected to result in a significant injury to the user. 2. a critical component is any component of a life sup port device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ag = 1.8v to 3.6v, 0 c to +70 c ah = 1.8v to 3.6v, ?40 c to +85 c v = 20-lead tssop p = 8-lead pdip g = rohs compliant lead free g = rohs compliant lead - free package blank = standard package. non lead-free v cc range blank = 5v 10% 2.5 = 2.5v to 5.5v 1.8 = 1.8v to 3.6v temperature range blank = 0 c to +70 c i = ?40 c to +85 c package s8 = 8-lead soic v20 = 20-lead tssop p = 8-lead pdip

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